Conventionally, it has been a popular method to sense current flowing through a switching transistor or a synchronous circuit rectifier transistor of a switching regulator, which forms a DC-DC converter, by sensing a voltage across a resistor which is inserted in series with the switching transistor or the synchronous circuit rectifier transistor.
Since the resistor in the method uses a lot of electricity, power conversion efficiency is decreased. Moreover, an additional step such as wave trimming etc. becomes necessary to sense current with a high degree of accuracy because of a low setup accuracy of a resistance included in a semiconductor.
FIG. 1 shows a schematic drawing showing a conventional circuit for sensing current. The shown circuit is arranged in order to resolve the problem described above and is disclosed in, for example, patent document 1.
The circuit shown in FIG. 1 senses that the current value of the current flowing through a switching transistor M101, which is formed of a PMOS transistor, reaches a predetermined value. PMOS transistors M103 and M104 are connected to the switching transistor M101 in parallel to each other. The PMOS transistor M103 of which a gate is connected to the GND, is in a conduction state, i.e. on-state. The PMOS transistor M104 of which a gate is connected to a gate of the switching transistor M101, is turned on/off in synchronization with the switching transistor M101.
A PMOS transistor M105 of which a source is connected to an input power source Vin and a gate thereof is connected to the GND, is in a conduction state, i.e. on-state. PMOS transistors M106˜M109 are connected to form a cascade current mirror circuit. A source of the PMOS transistor M106 is connected to a drain of the PMOS transistor M103, and a drain of the PMOS transistor M106 is connected to a source of the PMOS transistor M108. A source of the PMOS transistor M107 is connected to a drain of the PMOS transistor M105, and a drain of source of the PMOS transistor M107 is connected to a source of the PMOS transistor M109.
Each gate of the PMOS transistors M106 and M107 is connected to a drain of the PMOS transistor M108. Each gate of the PMOS transistors M108 and M109 is connected to one end of a resistor R101 of which the other end is connected to the drain of the PMOS transistor M108. A current source 101 is inserted between the other end of the resistor R101 and the GND. A current source 102 is inserted between a drain of the PMOS transistor M109 and the GND.
In such a circuit configuration described above, when the current value of the current flowing through the switching transistor M101 is relatively low, a drain voltage of the PMOS transistor M103 is increased to a voltage close to input voltage Vin. And then the current flowing through the PMOS transistors M106 and M108 becomes greater than the current flowing through the PMOS transistors M107 and M109. Thus, a voltage of an excess current output terminal OUTa becomes closer to the GND voltage. On the other hand, when the current flowing through the switching transistor M101 starts to increase, the current flowing through the PMOS transistors M103 and M104 starts to increase. And then the drain voltage of the PMOS transistor M103 starts to decrease. When the drain voltage of the PMOS transistor M103 becomes lower than the drain voltage of the PMOS transistor M105, the excess current output terminal OUTa outputs a high level signal.
[Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-78427
According to the circuit shown in FIG. 1, since the current source 101 is used as a reference current source of the current mirror circuit, current i101 is supplied from the current source 101 to the PMOS transistor M103. Thus, in a condition where the current flowing through the switching transistor M101 is relatively low, it becomes necessary to make on resistance of the PMOS transistor M105 larger than that of the PMOS transistor M103, by making size of PMOS transistor M105 much smaller than that of the PMOS transistor M103, in order to make the current flowing through the PMOS transistors M107 and M109 smaller than the current flowing through the PMOS transistors M106 and M108, and to make the drain voltage of the PMOS transistor M105 lower than the drain voltage of the PMOS transistor M103.
As the current flowing through the switching transistor M101 increases and the drain voltage of the PMOS transistor M103 decreases, a gate voltage of the PMOS transistor M106 decreases because a gate-source voltage of the PMOS transistor M106 is unchanged. Since the gate of the PMOS transistor M107 is connected to the gate of the PMOS transistor M106, a gate voltage of the PMOS transistor M107 decreases and current flowing through the PMOS transistors M107 and M109 increases.
Since the drain voltage of the PMOS transistor M105 decreases with the increase of the current flowing through the PMOS transistors M107 and M109, a fluctuation of the gate-source voltage of the PMOS transistor M107 is small and an increasing rate of the current flowing through the PMOS transistors M107 and M109 is slow. Thus, a gain of the current mirror circuit when used as a comparator may be lowered. Then an accuracy of sensed current may be lowered and response speed may become slow.
Further, current level for sensing may be fluctuated because of an influence of sensing delay time of a current sensing circuit, when an input voltage is fluctuated or an output voltage is changed.